From DE 26 25 917 A1 there is known a semi-conductor device including a semi-conductor body with four layers of alternate P and N conducting types, these layers constitute a thyristor whose outermost layers form emitter junctions with adjacent layers. The semi-conductor body also includes an integrated field effect transistor part for bridging one of the emitter junctions of the thyristor. The source and drain of the field effect transistor include regions of the same conductivity type, one of which forms the emitter layer adjacent to the bridged emitter junction and the other of which comprises a region ohmically connected to the layer adjacent to the emitter layer and of the same type of conductivity as the emitter layer. The field effect transistor has a control electrode and a protective diode is provided in the semi-conductor body for limiting voltage between the control electrode of the field effect transistor and the semi-conductor body. The thyristor is arranged for optical ignition. To provide a good ohmic contact between a gate electrode for ignition of the thyristor and a P-type base layer a highly doped P+-type well region is provided below the electrode.
From EP 0 002 840 A1 there is known a thyristor wherein a N-type cathode emitter zone and a highly doped P+-type gate region is embedded in a P-type base layer. The depth of the P+-type gate region and of the N-type cathode emitter zone is about 15 μm.
From EP 0 283 788A1 there is known a GTO thyristor wherein a highly doped P+-region is arranged below a P-doped base region. The dopant concentration of this P-base region is lower than the dopant concentration in the previously mentioned P+-region The advantage of this is that the breakdown voltage between an N-emitter zone and the P-base region is largely independent of the depth of penetration of the N-emitter zone and of the selection of the transverse conductivity of the P-base zone.
From U.S. Pat. No. 5,369,291 A there is known a voltage controlled thyristor, which includes an intrinsic layer of material between an anode and a cathode. A gate region between the intrinsic layer and the cathode comprises a lightly doped P type layer with more heavily doped P type regions extending through the lightly doped layer into the intrinsic layer. The more heavily doped P type regions are interspersed among shallower N doped regions of the cathode.
From JP 3 334509 B2 there is known a gate-turn-off thyristor which enables uniform turn-off operation in respective regions, regardless of the position of a cathode electrode to thereby improve its shutdown immunity. The thyristor includes an N emitter layer on a cathode side, a P base layer, an N base layer and a P emitter layer on an anode side. The N emitter layer is made up of a plurality of regions mutually separated in the P base layer and elongated in a radius direction, and a cathode electrode is deposited on each of the separated regions of the emitter layer. Gate electrodes are deposited on the P base layer, so as to surround the respective regions of the N emitter layer. A gate lead metal in the form of a plate is formed on the nearly the entire surface of the gate electrodes as opposed thereto, and is provided therein with a plurality of openings, so as to surround the regions of the cathode electrode and to be electrically connected to the gate electrodes.
From JP H04 320374 A it is known to turn off a high anode current in a thyristor in a short time by providing an insulating film on a gate electrode and setting the sum of thickness of metal thin film and the insulating film thicker than a cathode metal electrode. An electrode of about 15p m thick is formed on the anode surface through aluminum deposition. Furthermore, aluminum is deposited by about 9 μm on the cathode surface to form a thin cathode electrode. Aluminum is further deposited by about 2 μm on the cathode surface to form first and second metal gate electrodes. At the same time, aluminum is deposited on the cathode electrode by about 11 μm. The cathode side surface is then covered with an insulator except the external terminal take-out parts of the cathode electrode and a gate electrode. The cathode electrode can be pressed by means of a thermal buffer having no groove and characteristics equivalent or better than those of GTO having a hybrid structure can be achieved.
A known turn-off power semiconductor device is the bi-mode gate commutated thyristor (BGCT) as shown in FIGS. 1 to 3. FIG. 1 shows the device in top view and FIG. 2 shows the device in cross-section taken along line c′c in FIG. 1. The BGCT comprises in a single wafer 1 a plurality of gate commutated thyristor (GCT) cells 2 electrically connected in parallel to one another. In the BGCT shown in FIGS. 1 and 2 each of the GCT cells 2 is made up from three cathode electrodes 3 in form of a cathode metallization layer, an n+-doped cathode layer comprising three strip-shaped cathode segments 4, a p-doped base layer 5, an n−-doped drift layer 6, an n-doped buffer layer 7, a p+-doped anode layer 8 and an anode electrode 9 in form of an anode metallization layer. The GCT cells 2 also include a gate electrode 10 in form of a gate metallization layer, which is in contact with the p-doped base layer 5. The gate metallization layer is arranged in a plane, which is below the plane, in which the cathode electrodes 3 are arranged, so that the gate electrodes are vertically separated from the cathode electrodes 3. The BGCT includes one single gate contact 11 in the form of an annular metallic region in the center of the wafer 1. The gate contact 11 is in direct contact with the gate metallization layer, so that the gate contact 11 and the gate electrodes 10 of all GCT cells 2 are connected electrically and thermally with each other. The BGCT comprises a plurality of diode cells 12 distributed between the GCT cells 2. The diode cells 12 are electrically connected in parallel to one another and to the GCT cells 2, albeit with opposing forward direction. Each diode cell 12 includes an anode electrode 17, a p-doped anode layer 13, an n+-doped cathode layer 14, and a cathode electrode 16, wherein the p-doped anode layer 13 and the n+-doped cathode layer 14 are separated by the n−-doped drift layer 6 and the n-doped buffer layer 7. Neighboring GCT cells 2 and diode cells 12 are separated by multiple separation regions 15.
FIG. 3 shows a partial cross-section of a segment of the BGCT shown in FIG. 2. There are shown two cathode segments 4 and a gate electrode 10 between these two cathode segments 4 in FIG. 3 in cross-section. On the main side surface of the wafer 1 an oxide passivation layer 19 is formed. The metallization layer forming the cathode electrodes 3 is in contact with the cathode segments 4 through first openings 20 in the oxide passivation layer 19 and the metallization layer forming the gate electrodes 10 is in contact with the base layer 5 through second openings 21 in the oxide passivation layer 19. A polyimide passivation layer 18 is formed between the cathode electrodes 3 on the oxide passivation layer 19 and the gate electrodes 10.
In FIGS. 4A to 4C there are illustrated steps of a manufacturing method for defining the cathode segments 4 in the before-described BGCT. As shown in FIG. 4A a patterned protection oxide layer 25 is formed on the main surface of a wafer, which includes the p-doped base layer 5 and a thin highly n+-doped layer 26 formed on the p-base layer 5. In a next step, the thin highly n+-doped layer 26 and part of the p-doped base layer 5 is etched by about 13 μm using the patterned protection oxide layer 25 as an etching mask to obtain a structure as shown in FIG. 4B. In a subsequent drive-in step, the n-type dopant of the structured highly n+-doped layer 26′ is driven into the p-doped base layer 5 to obtain the cathode segments 4 as in the final structure shown in FIG. 3.
In all subsequent process steps of the method for manufacturing the BGCT, namely in the steps of forming the oxide passivation layer 19, the cathode electrodes 3, the gate electrodes 10 and the polyimide passivation layer 18, there is the problem that respective layers including the photoresist layers used for structuring the layers have to be deposited on a structured surface of the wafer 1 having steps in the wafer surface. Accordingly, issues related to step coverage of these layers can result. Also, the steps in the wafer surface reduce the space available for the cathode electrodes 3, and, therefore, limit the electrical and thermal contact. Besides the limitation of the electrical and thermal contact, the steps in the wafer surface make it impossible to reduce certain lateral dimensions and limit minimum dimensions as well as the density of the cathode segments 4. For example, the distance between each first opening 20 (i.e. cathode opening) and a neighbouring second opening 21 (i.e. gate opening) cannot be made smaller than 50 μm due to the step in the wafer surface between each first opening 20 and a neighbouring second opening 21.
In view of the above, it is the object of the invention to provide a turn-off power semiconductor device, which can overcome the above-described problems in the prior art. In particular, it is an object of the invention to provide a turn-off power semiconductor device having a plurality of thyristor cells, in which the density of separate cathode regions and/or the density of thyristor cells can be increased, any issues related to step coverage can be avoided and an electrical and thermal contact area can be increased, while ensuring a good performance of the turn-off power semiconductor device especially during turn-off.
The object of the invention is attained by a turn-off power semiconductor device according to claim 1.
In the turn-off power semiconductor device of the invention, interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. Due to this feature of the turn-off power semiconductor device of the invention, all issues related to step coverage in the turn-off power semiconductor device known from the prior art are avoided. Further, the flat design results in more available space for the cathode metallization so that the electrical and thermal contact is improved. Lateral dimensions can be reduced compared to the turn-off power semiconductor device of the prior art and, therefore, the density of the cathode regions and/or the density of the thyristor cells in the device can be increased.
In addition, the turn-off power semiconductor device of the invention differs from the above described known turn-off power semiconductor device in that the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of a depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 μm from the cathode region. The highly doped gate well region results in a reduced serial resistance between the gate contact and a region just below the cathode region, thus allowing to increase the commutation current and to thereby improve the turn-off performance, while the lower doped portion of the base layer extending from the cathode region and arranged between the cathode region and the gate well region allows a sufficiently high gate-cathode blocking voltage (VGR) which is required for proper turn-off.
In the invention, the base layer includes a compensated region, which is arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the doping concentration in the compensated region is at least 0.4. With such feature, the gate-cathode blocking voltage (VGR) can be increased compared to a device without such highly compensated region.
Further developments of the invention are specified in the dependent claims.
In an exemplary embodiment, the depth of the gate well region is at least the depth of the cathode region. Exemplarily, the depth of the gate well region is at least 5 μm, more exemplarily at least 10 μm.
In an exemplary embodiment, the depth of the cathode regions is at least 10 μm, exemplarily at least 15 μm.
In an exemplary embodiment, the doping concentration of a portion of the base layer, which is arranged directly adjacent to the first main side and which is arranged between the cathode region and the gate well region, is increasing with increasing distance from the first main side. In such exemplary embodiment, a high gate-cathode blocking voltage (VGR) can be ensured. For proper turn-off of the device a gate-cathode blocking voltage of at least 20 V is preferable.
Exemplarily, the compensated region extends from the first main side to a depth, which is at least half of the depth of the cathode region. Specifically, the compensated region may extend from the first main side to a depth of at least 10 μm, exemplarily at least 15 μm.
In an exemplary embodiment, the cathode electrode has a thickness of at least 10 μm, exemplarily a thickness of at least 15 μm. The larger the distance between the level of the upper surface of the cathode metallization and the level of the upper surface of the gate metallization is, the better is the separation between a molybdenum (Mo) disc, which is used for contacting the cathode metallization layer in a standard press pack, and the gate metallization. A sufficient separation between the molybdenum disc and the gate metallization can avoid that small particles can cause a short circuit between the molybdenum disc and the gate metallization.
In an exemplary embodiment, a space between neighboring cathode electrodes is filled up with an insulating layer, and a continuous cathode contact layer is arranged on top of the cathode electrodes and the insulating layer to be in direct contact with the cathode electrodes and the insulating layer. In such exemplary embodiment, the thermal performance is improved. The continuous cathode contact layer on top of the cathode electrodes and on top of the insulating layer can increase the contact area and thus reduce the thermal resistance. In addition, such embodiment allows to bond the molybdenum disc to the front-side, e.g. by low-temperature bonding using Ag micro- or nano-particles. With such design, the turn-off power semiconductor device could even be used in modules, where the cathode contact is wire-bonded. Moreover, in such embodiment small particles cannot cause a short circuit between the molybdenum disc and the gate metallization.
The object is also attained by a method for manufacturing a turn-off power semiconductor device according to claim 10.
The reference signs used in the figures and their meanings are summarized in the list of reference signs. Generally, similar elements have the same reference signs throughout the specification. The described embodiments are meant as examples and shall not limit the scope of the invention.